Feb 18, 2024 · x86 and amd64 instruction reference. Derived from the December 2023 version of the Intel® 64 and IA-32 Architectures Software Developer’s Manual. Last updated 2024-02-18. THIS REFERENCE IS NOT PERFECT. It's been mechanically separated into distinct files by a …

Description ¶ . Computes the effective address of the second operand (the source operand) and stores it in the first operand (destination operand). The source operand is a memory address (offset part) specified with one of the processors addressing modes; the destination operand is a general-purpose register.

Description ¶ . Saves procedure linking information on the stack and branches to the called procedure specified using the target operand. The target operand specifies the address of the first instruction in the called procedure.

This UNOFFICIAL, mechanically-separated, non-verified reference is provided for convenience, but it may be inc omp lete or b r oke n in various obvious or non-obvious ways. Refer to Intel® 64 and IA-32 Architectures Software Developer’s Manual for anything serious.Intel® 64 and IA-32 Architectures Software Developer’s Manual for anything serious

#GP(0) If the return code or stack segment selector is NULL. If the return instruction pointer is not within the return code segment limit. If returning to 32-bit or compatibility mode and the previous SSP from shadow stack (when returning to CPL <3) …

Description ¶ . Computes the bit-wise logical AND of first operand (source 1 operand) and the second operand (source 2 operand) and sets the SF, ZF, and PF status flags according to the result.

Opcode Instruction Op/En 64-Bit Mode Compat/Leg Mode Description; EB cb: JMP rel8: D: Valid: Valid: Jump short, RIP = RIP + 8-bit displacement sign extended to 64-bits.

Opcode/Instruction Op/En 64/32 bit Mode Support CPUID Feature Flag Description; 66 0F 38 F8 /r MOVDIR64B r16/r32/r64, m512: A: V/V: MOVDIR64B: Move 64-bytes as direct-store with guaranteed 64-byte write atomicity from the source memory operand address to destination memory address specified as offset to ES segment in the register operand.

Description ¶ . Loads a byte, word, or doubleword from the source operand into the AL, AX, or EAX register, respectively. The source operand is a memory location, the address of which is read from the DS:ESI or the DS:SI registers (depending on the address-size attribute of the instruction, 32 or 16, respectively).

1. If the paging structures map the linear address using a page larger than 4 KBytes and there are multiple TLB entries for that page (see Section 4.10.2.3, “Details of TLB Use,” in the Intel ® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3A), the instruction invalidates all of them.. Real-Address Mode Exceptions¶