the positive going transition of the clock pulse. CLEARand PRESET are independent of the clock andaccomplishedby alowontheappropriate input. ... Minimum Pulse Width (CLOCK) 2.0 18 75 95 110 4.5 6151922ns 6.0 6131619 tW(L) Minimum Pulse Width (CL, PR) 2.0 21 75 95 110 4.5 7151922ns 6.0 6131619 tsMinimum Set-up Time

The CHT-7474 can operate with supply voltages from 3.3 to 5V (±10%). Features • Qualified from -55 to +225°C (Tj) • 3.3 to 5V (±10%) supply voltages • Latchup-free at any supply and tem-perature condition • Validated at 225°C for 30000 hours (CDIL14) and 20000 hours (CSOIC16) (and still on-going)

For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.

7474 Datasheet(HTML) 2 Page - Fairchild Semiconductor : zoom in zoom out 2 / 5 page. ... ↑) indicates the rising edge of the clock pulse is used for reference. Note 4: T A = 25°C and V CC = 5V. Electrical Characteristics. ... Pulse Width. Clock HIGH. 30 (Note 4) Clock LOW. 37. ns.

the positive going edge of the clock pulse. The triggering occurs at a voltage level and is not directly related to the transition time of the rising edge of the clock. The data on the D input may be changed while the clock is LOW or HIGH without affecting the outputs as long as the data setup and hold times are not violated. A LOW logic level on

Part #: 7474. Download. File Size: 51Kbytes. Page: 5 Pages. Description: Dual Positive-Edge-Triggered D-Type Flip-Flops with Preset, Clear and Complementary Outputs. Manufacturer: Fairchild Semiconductor.

The CMT-7474 is a dual positive-edge-triggered D type Flip-flop. Data on the D input is transferred to the output on a rising edge of the clock impulse. Rn and Sn are asynchronous reset and set. On a low state, they operate on the outputs regardless of the other inputs. The CMT-7474 can operate with supply

The 74F74 is a dual positive edge-triggered D-type flip-flop featuring individual data, clock, set, and reset inputs; also true and complementary outputs. Set (SD) and reset (RD) are asynchronous active low inputs and operate independently of the clock input.

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP. The SN54 /74LS74A dual edge-triggered flip-flop utilizes Schottky TTL cir - cuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs.

DM7474 Dual Positive-Edge-Triggered D Flip-Flops with Preset, Clear and Complementary Outputs. General Description. This device contains two independent positive-edge-triggered D flip-flops with complementary out- puts. The information on the D input is accepted by the flip-flops on the positive going edge of the clock pulse.